1. Field of the Invention
The present invention relates to memories generally and, more specifically, to static random access memories.
2. Description of the Related Art
Static random access memory (SRAM) is ubiquitous. It is used in everything from computer memory to digital watches. There are instances where it is desirable to clear the memory, i.e., write all zeros, into the memory. The typical approach is to sequentially write all, or a defined subset of all, of the memory cells to write predefined data, e.g., a zero, in those cells. While this will insure that those memory cells are cleared, significant amount of time might be required to individually access all of the memory cells to be cleared. An alternative approach is to “flash clear” the memory by simultaneously forcing all the memory cells into a predetermined state. One approach to implementing a flash clear is to simultaneously activate all of the word-lines in the memory and concurrently forcing all the bit-lines to reference voltage. One drawback for this approach is relatively high power supply current consumption that might significantly degrade the reliability of the chip due to electromigration of conductors on the chip and the high heat generated during the flash clear.
Another approach is disclosed in U.S. Pat. No. 7,333,380, incorporated herein by reference in its entirety. As shown in FIG. 1 of the patent, pull-down and/or pull-up of a memory cell latch is forced such that it alters data in a memory cell. Because ground is provided to a portion of the latch in each memory cell through an inverter (IVC), this approach has several drawbacks. For the portion of the latch driven by the inverter IVC, there are two series-connected transistors (one PMOS device in the inverter (not shown), and one NMOS device TN1) used during the clearing of the memory cell. At today's low operating voltages, e.g., less than 1 volt, clearing all of the memory cells might not be guaranteed due to an insufficient voltage (headroom) occurring on node ND1 to assure switching of transistors TN2 and TP2 to a desired state because of manufacturing variations in the electrical characteristics of the PMOS and NMOS devices in the memory cells.
Thus, it is desirable to provide a static memory design that allows for quickly clearing the memory while avoiding excessive power supply current consumption and remain functional at low operating voltages.